1. Field of the Invention
The present invention relates generally to semiconductor devices and particularly to a configuration of an output circuit driving an external bus signal line in response to an internal signal. More specifically, the present invention relates to a configuration of signal output circuitry of a semiconductor device supplied with an output power supply voltage used for outputting a signal and an external power supply voltage used for driving an internal circuit, separately.
2. Description of the Background Art
FIG. 11 schematically shows a configuration of a main portion of a conventional semiconductor device. The semiconductor device 900 includes an internal power supply circuit 901 generating various kinds of internal voltage from an external power supply voltage EXVDD, a memory circuit 902 operating in accordance with the various kinds of internal voltage generated by internal power supply circuit 901, and an output circuit 903 receiving an externally supplied output power supply voltage VDDQ as an operating power supply voltage to buffer data read from memory circuit 902 and externally output the data.
Internal power supply circuit 901 generates an internal power supply voltage used by memory circuit 902 as an operating power supply voltage, an intermediate voltage, a reference voltage and others. For the purpose of simplifying the figure, however, FIG. 11 typically shows a peripheral power supply voltage VDDP generated by internal power supply circuit 901. Normally, external power supply voltage EXVDD is, for example, not lower than 2.5V and output power supply voltage VDDQ is, for example, 1.8V. When external power supply voltage EXVDD is 2.5V, external power supply voltage EXVDD is used as peripheral power supply voltage VDDP. In this case, an array power supply voltage used by a memory cell array included in memory circuit 902 is generated by down-converting external power supply voltage EXVDD. Peripheral power supply voltage VDDP is indicated so as to distinguish peripheral power supply voltage VDDP from external power supply voltage EXVDD in the description.
Memory circuit 902 includes the memory cell array, a row and column select circuit selecting a memory cell of the memory cell array, an internal data read circuit and others.
By applying output power supply voltage VDDQ exclusively to output circuit 903, memory circuit 902 can be stably operated with internal power supply voltage VDDP generated from external power supply voltage EXVDD, even if the output power supply voltage VDDQ varies due to an operation of output circuit 903 consuming output power supply voltage VDDQ. Even when multi-bit data DQ is generated to be transferred, memory circuit 902 can be operated stably without affect due to variation of output power supply voltage VDDQ.
Furthermore, with output power supply voltage VDDQ exclusively supplied to output circuit 903, output circuit 903 can be supplied with an operating power supply voltage with sufficiency, and output circuit 903 can thus be operated in stable manner.
FIG. 12 schematically shows a configuration of a portion of output circuit 903 that is related to outputting of one bit of data. In FIG. 12, output circuit 903 includes an NAND circuit 906 receiving internal read data RD read from an internal read circuit 905 included in memory circuit 902 and an output enable signal OEM, a gate circuit 907 receiving internal read data RD and output enable signal OEM, a level conversion circuit 908 converting the amplitude of a signal output from NAND circuit 906 to the level of output power supply voltage VDDQ, a level conversion circuit 909 converting the amplitude of a signal output from gate circuit 907 to the level of external power supply voltage EXVDD, an inverter circuit 910 inverting a signal output from level conversion circuit 909, and an output buffer circuit 912 driving an output node 920 in response to a signal output from level conversion circuit 908 and a signal output from inverter 910.
Internal read circuit 905 is included in memory circuit 902 shown in FIG. 11, includes a preamplifier circuit and others, and receives peripheral power supply voltage VDDP as an operating power supply voltage and generates internal read data RD having the amplitude of the peripheral power supply voltage VDDP level.
NAND circuit 906 and gate circuit 907 receive peripheral power supply voltage VDDP as an operating power supply voltage. When output enable signal OEM is at a logical low level or L level, NAND circuit 906 outputs a signal of a logical high level or H level. When output enable signal OEM attains an H level, NAND circuit 906 operates as an inverter to invert internal read data RD.
When output enable signal OEM is at L level, gate circuit 907 outputs a signal of the H level and when output enable signal OEM attains the H level, gate circuit 907 operates as a buffer circuit and generates an output signal in accordance with internal read data RD.
Level conversion circuit 908 receives output power supply voltage VDDQ as an operating power supply voltage and level conversion circuit 909 receives external power supply voltage EXVDD as an operating power supply voltage.
Level conversion circuits 908 and 909 simply perform the voltage level (or amplitude) conversion and do not perform conversion in logical level.
Output buffer circuit 912 includes a p-channel MOS transistor (an insulated gate field effect transistor) TP connected between an output power supply node and an output node 920 and having a gate thereof receiving a signal output from level conversion circuit 908, and an n-channel MOS transistor TN connected between output node 920 and a ground node and having a gate thereof receiving a signal output from inverter circuit 910.
When output enable signal OEM is at L level, NAND circuit 906 and gate circuit 907 each output a signal of the H level, and level conversion circuit 908 outputs a signal at the output power supply voltage VDDQ level and level conversion circuit 909 outputs a signal at the external power supply voltage EXVDD level. Inverter 910, receiving external power supply voltage EXVDD as an operating power supply voltage and inverting a signal output from level conversion circuit 909, outputs a signal of the L level.
MOS transistors TP and TN in output buffer circuit 912 are both turned off and thus output buffer circuit 912 attains an output high impedance state.
When output enable signal OEM attains the H level, NAND circuit 906 operates as an inverter, while gate circuit 907 operates as a buffer circuit. When internal read data RD is at H level, NAND circuit 906 outputs a signal of L level and gate circuit 907 outputs a signal of H level. Thus, level conversion circuit 908 outputs a signal of L level and inverter circuit 910 outputs a signal of L level. Thus, MOS transistors TP and TN in output buffer circuit 912 are turned on and off, respectively. In this state, output node 920 is driven to the output power supply voltage VDDQ level via MOS transistor TP.
When internal read data RD is at H level, NAND circuit 906 outputs a signal of H level and gate circuit 907 outputs a signal of L level. In response, inverter 910 outputs a signal of the external power supply voltage EXVDD level and output buffer circuit 912 has MOS transistors TP and TN turned off and on, respectively, and output node 920 is driven via MOS transistor TN to the ground voltage level. By applying a signal of the external power supply voltage level to the gate of MOS transistor TN via inverter circuit 910, the current driving capability of MOS transistor TN is increased to quickly discharge output node 920 to the ground voltage level.
FIG. 13 shows an exemplary configuration of level conversion circuit 908. In FIG. 13, level conversion circuit 908 includes an inverter 908a receiving a signal SIN output from NAND circuit 906, an n-channel MOS transistor 908b connected between an internal node NA and a ground node and having a gate thereof receiving signal SIN output from the NAND circuit, an n-channel MOS transistor 908c connected between an internal node NB and a ground node and having a gate thereof receiving a signal output from inverter 908a, a p-channel MOS transistor 908d connected between an output power supply node and internal node NA and having a gate thereof connected to internal node NB, and a p-channel MOS transistor 908e connected between an output power supply node and internal node NB and having a gate thereof connected to internal node NA. A signal SOUT output from level conversion circuit 908 is generated at internal node NB.
When signal SIN is at H level, MOS transistors 908b and 908c turn on and off, respectively. Thus, internal node NA is discharged via MOS transistor 908b to reduce in voltage level. In response, MOS transistor 908e turns on to charge internal node NB, and internal node NB is increased in voltage level to the output power supply voltage VDDQ level.
When internal node NB attains the output power supply voltage level, MOS transistor 908d turns off. Signal SIN of the peripheral power supply voltage VDDP level is thus converted to signal SOUT of the output power supply voltage VDDQ level.
When signal SIN is at L level, MOS transistors 908b and 908c turn off and on, respectively. In this state, internal node NB is discharged via MOS transistor 908c and is reduced in voltage level. In response, MOS transistor 908d turns on to charge internal node NA to the output power supply voltage VDDP level, and MOS transistor 908e responsively turns off. Thus, in this state, internal node NB outputs the signal SOUT of L level.
As described above, level conversion circuit 908 converts signal SIN of the peripheral power supply voltage VDDP level in amplitude to a signal of the VDDQ level in amplitude and does not perform logical level conversion.
The use of level conversion circuit 908 allows an internal circuit to be driven with the peripheral power supply voltage VDDP level and output buffer circuit 912 to generate a signal of the output power supply voltage level.
Furthermore, if peripheral power supply voltage VDDP is equal to external power supply voltage EXVDD and higher than output power supply voltage VDDQ, a signal applied to output buffer circuit 912 is converted in amplitude to the output power supply voltage level to equalize the rising and falling characteristics of the signal to the output buffer circuit. It is aimed to equalize the rising and falling characteristics in driving the output node by the output buffer circuit 912.
FIG. 14 schematically shows a configuration of a data processing system by way of example. In the processing system shown in FIG. 14, a processing unit 950, a semiconductor memory device 952 storing data used by processing unit 950 and a memory 954 separate from semiconductor memory device 952 are interconnected together through a bus 956.
Processing unit 950 receives power supply voltage VDDL and VDDQ as operating power supply voltages. Semiconductor memory device 952 receives power supply voltage EXVDD and VDDQ as operating power supply voltages. Memory 954 receives power supply voltage VDDL as an operating power supply voltage. When processing unit 950 transmits data to semiconductor memory device 952 through bus 956, processing unit 950 transfers a signal in accordance with output power supply voltage VDDQ to adapt the signal interface with semiconductor memory device 952.
In such a data processing system, if no access is made to semiconductor memory device 952 for a long period of time, processing unit 950 stops supplying external power supply voltage EXVDD at least to semiconductor memory device 952, via a power supply management unit (not shown). Processing unit 950 uses data stored in memory 954 to execute a processing.
As data/a signal is transferred between memory 954 and processing unit 950 through bus 956, output buffer circuit 912 shown in FIG. 12 is required to maintain an output high impedance state even when semiconductor memory device 952 is stopped of supplying external power supply voltage EXVDD while being supplied with output power supply voltage VDDQ. A MOS transistor turns off when its gate to source voltage goes below a threshold voltage in absolute value. Thus, for example in the configuration of FIG. 13, if peripheral power supply voltage VDDP generated from external power supply voltage EXVDD drops in level in response to stopping of supplying external power supply voltage EXVDD, there may be caused a case where the signal SIN set to H level in a standby state thereof is not discharged to the ground voltage level and the signal SIN is held at an intermediate voltage level. Similarly, the output signal from the inverter 908a might be held at an intermediate voltage level.
In this case, if level conversion circuit 908 has MOS transistors 908b and 908c both turned on or both turned off, internal nodes NA and NB has voltage at an uncertain level, and level conversion circuit 908 outputs an signal SOUT that is not held at output power supply voltage VDDQ level but at an intermediate voltage level. If such state is caused, MOS transistor TP in output buffer circuit 912 would possibly supply a current to output node 920.
Similarly also in the arrangement of FIG. 12, if supplying of external power supply voltage EXVDD is stopped, the output signal of inverter 910 could not discharged fully to the ground voltage level, and level conversion circuit 909 would have the output signal floating in level to an intermediate voltage level. In response, inverter 910 enters a state of outputting a signal held at an intermediate voltage level and the discharging MOS transistor TN turns conductive. Thus, in this state also, output buffer circuit 912 has MOS transistor TN turned conductive and drives output node 920 towards the ground voltage level, and output buffer circuit 912 thus does not enter the output high impedance state.
In semiconductor memory unit 952, if output buffer circuit 912 is set into a state different from the output high impedance state, a signal/data transferred in between memory 954 and processing unit 950 would be adversely affected by data outputted from output buffer circuit 912, and thus, a signal/data can not be transferred accurately.
The following state is considered. Processing unit 950 and semiconductor memory device 952 are interconnected together via bus 956 and processing unit 950 is interconnected to memory 954 via a different bus. In addition, the bus interconnecting processing unit 950 and semiconductor memory device 952 has a signal line terminated to a voltage different in level from output power supply voltage VDDQ. Even in such state, if output buffer circuit 912 is set to a state different from the output high impedance state, a current would flow between output buffer circuit 912 and a terminating power source and current consumption thus disadvantageously increases.
An object of the present invention is to provide a semiconductor memory device having an output buffer circuit reliably is held at an output high impedance state even if an output power supply voltage is interrupted while an output power supply voltage is supplied.
A semiconductor device according to a first aspect of the present invention includes: a first output drive signal generation circuit receiving a first power supply voltage as an operating power supply voltage and for generating a first output drive signal in response at least to an internal signal; a first latch circuit receiving a second power supply voltage as an operating power supply voltage and latching and transferring the first output drive signal; and a first output transistor receiving the second power supply voltage as an operating power supply voltage and in response to a signal output from the first latch circuit for driving an output node.
A semiconductor device according to a second aspect of the present invention includes first circuitry receiving a first power supply voltage as an operating power supply voltage thereof and generating a first signal in accordance with a received signal, and second circuitry receiving a second power supply voltage as an operating power supply voltage thereof and generating a second signal in accordance with the first signal. The second circuitry includes a latch circuit receiving the first signal at an input and latching a signal voltage at the input.
According to the arrangement of the present invention, the latch circuit is provided which receives the second power supply voltage as the operating power supply voltage and the output transistor or an output driving circuit is driven in accordance with the output signal of the latch circuit. Even if supplying of the first power supply voltage is interrupted, the latch circuit latches the state of the signal immediately before the interruption of supply of the first power supply voltage. Thus, the output transistor or the output driving circuit can be held in the state immediately before the interruption of the first power supply voltage to hold the output high impedance state. Accordingly, the output circuit can be reliably held in the output high impedance state upon interruption of the supply of the first power supply voltage, to prevent the collision of a signal/data on an external bus from occurring.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.